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M88DR5RCD01 - DDR5 Registering Clock Driver (RCD)

M88DR5RCD01 is a two-channel, single-ended DDR5 registering clock driver (RCD) with parity for driving and buffering the Command/Address (CA) bus, Chip Selects, and clock between the host controller and the DDR5 SDRAMs. It is compliant with JEDEC DDR5 RCD01 specification, and supports RDIMM and LRDIMM modes with the operation speed up to DDR5-4800. The RCD chip provides 1:2 registering buffer for 7-bit DDR or SDR Command/Address inputs and 2-bit control signals for each channel, with the operating voltage of 1.1V (VDD). M88DR5RCD01 can be used independently as a central buffer on an RDIMM or used in conjunction with specified number of DDR5 Data Buffers (DB) on an LRDIMM to provide DDR5 memory interface solution with high capacity, high speed and low power for the next-generation server platforms.


Compliant with JEDEC DDR5RCD01 specification

Speed up to DDR5-4800

Two-channel, 1:2 registering buffer for 7-bit DDR or SDR Command/Address inputs and 2-bit control signals per channel

Integrated PLL clock driver distributing one differential clock signal to five differential clock pairs per channel

VDD voltage support: 1.1V

Dual chip selects support

Parity checking across CA and DPAR inputs separately on two sub-channels

4-tap Decision Feedback Equalization (DFE) on DCA host-interface receivers

Rx loopback mode support for debugging, testing and/or training purposes

CS, CA and DFE calibration training modes support

Output characteristics configurable through register words

Sideband interface support

Several power saving modes support: PDE power down mode, DRAM power down mode with ODT control, Clock stop power down mode.

Low power consumption

Green package: 240-ball Fine-pitch Ball Grid Array (FBGA)

High-performance DDR5 RDIMM and LRDIMM

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