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M88SSTE32882H0 - DDR3 Register Buffer (VDD = 1.5V / 1.35V / 1.25V)

M88SSTE32882H0 is a 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity for DDR3 RDIMM applications. It is compliant with JEDEC SSTE32882 specification and supports speed up to DDR3-1866. 

The device buffers the input address and control signals and redrives two copies per signal. Based on control register settings the device can change its output characteristics to match different DIMM net topologies.

The device is compliant with the JEDEC specification. It also provides some extra features such as register read mechanism (patented) to monitor the status of the device without changing its existing pinout, transparent mode to help check DRAM defects, and frequency change on the fly to save power, etc.


FeatureApplication

Compliant with JEDEC SSTE32882 specification

28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1 registering buffer for DDR3 applications

Integrated PLL clock driver distributing one differential clock pair to 4 differential pairs

Speed up to DDR3-1866

VDD voltage supported: 1.5V / 1.35V / 1.25V

Quad-rank DRAMs supported (quad chip selects mode)

Parity checking on command and address signal inputs

Output characteristics configurable through control registers

1T/3T MRS timing

Pre-launch feature

Constant propagation delay against VT variations

Different power saving modes such as S3 low power mode, CK STOP mode, etc.

Register read operation to monitor the chip status (patented)

Transparent mode

Frequency change on the fly

Low power consumption

Green package: 176-ball TFBGA

High-performance DDR3 RDIMM server

High-performance computer platform 

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